Job Description

Jr. FPGA Engineer

Downtown Chicago - Onsite

About The Role:

We are seeking a Junior FPGA Engineer with SystemVerilog and Linux experience to design, simulate, and verify RTL for production hardware in a quality-focused engineering environment. Financial industry experience is a plus, but not required.

What You’ll Do:

• Design and develop RTL in SystemVerilog
• Translate design requirements into hardware solutions
• Build and maintain simulation testbenches
• Debug functional and timing issues
• Support FPGA synthesis, implementation & timing closure
• Integrate RTL with on-chip and external interfaces
• Participate in code reviews, regression testing & documentation
• Enhance build, verification & engineering infrastructure

What We’re Looking For:

Must Have:

• Bachelor's in EE, CE, CS, or related field + 3+ years RTL design (or 5+ years experience in lieu of degree)
• Proficiency in SystemVerilog/Verilog
• Strong knowledge of synchronous digital design (clocking, pipelining, FIFOs, CDC)
• Experience with HDL simulation and waveform debugging
• Strong Linux skills (Bash, Make, build scripts)
• Experience with Git, SVN, or ClearCase
• Basic scripting in TCL, Python, or similar

Nice To Have:

• Experience with cocotb, UVM, or constrained-random verification
• Familiarity with Xilinx Vivado or Intel Quartus
• Knowledge of AXI, AXI-Stream, Avalon, Ethernet, or PCIe
• Experience with high-speed FPGA designs and timing closure
• C/C++, kernel modules, or host-side driver experience
• Open-source HDL contributions or FPGA project portfolio

OOJ-1488G

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